1. Field of the Invention
The present invention relates to a circuit verifying method and a circuit verifying apparatus, and more particularly relates to a circuit verifying method and a circuit verifying apparatus, in which an operation of a semiconductor integrated circuit including asynchronous sequential circuits is verified.
2. Description of Related Art
When data transmission is carried out between sequential circuits on a transmission side and a reception side in an asynchronous sequential circuit, there is a case that an oscillation state of the output from the sequential circuit on the reception side is transferred to a sequential circuit or combinational circuit connected to a later stage. In this case, the logic of data outputted from the sequential circuit on the reception side cannot be determined. Such a state is referred to as a meta stable state, which causes a correct operation of a logic circuit containing the asynchronous sequential circuits. For this reason, in the design of the logic circuit, the operation verification in which the meta stable state is taken into consideration is carried out in a function simulation in an HDL (Hardware Description Language) level.
Such a function simulation is carried out under various conditions in which the period and phase of a clock signal supplied to each of the plurality of sequential circuits are changed. Usually, since the meta stable state generated in the sequential circuit on the reception side is generated in the sequential circuit on the transmission side, the function simulation is performed in which the meta stable state is taken into consideration. Thus, it is possible to increase a generation possibility of an erroneous operation in the logic circuit as a verification target circuit, and reproduce the same operation as the actual circuit and then detect the erroneous operation.
The detail of the simulation for verifying the operation of the asynchronous sequential circuit will be described below with reference to FIGS. 1A and 1B and FIG. 2A. The verifying operation in the conventional technique will be described below by using a function verification for an asynchronous sequential circuit shown in FIG. 5 as one example.
A sequential circuit FF2 on the reception side latches an enable signal EN1, i.e., an output signal Q1 from a sequential circuit FF1 on the transmission side at an active edge, e.g., a rising edge of an input clock signal CLK2. If the enable signal EN1 is a normal signal, namely, if the pulse width of the enable signal EN1 outputted from the sequential circuit FF1 is longer than one period of the clock signal CLK2, the sequential circuit FF2 latches the enable signal EN1 or the output signal Q1. At this time, the sequential circuit FF2 outputs an enable signal EN2. Thus, the asynchronous sequential circuit is determined to be in the normal state.
On the other hand, if the pulse width of the enable signal EN1 is shorter than one period of the clock signal CLK2 supplied to the sequential circuit FF2, namely, when an incorrect enable signal EN1 is supplied, the sequential circuit FF2 cannot latch the enable signal EN1, and output it to a combinational circuit CC2 at a next stage.
Referring to FIG. 1A, if the enable signal EN1 takes an incorrect logical data, the signal level of the enable signal EN1 or the output signal Q1 of the sequential circuit FF1 is always “0” at each of times T2, T8, . . . , or the rising edges of the clock signal CLK2. In this case, the enable signal EN2 outputted from the sequential circuit FF2 is always “0”. In this way, the asynchronous sequential circuit as a verification target circuit is detected to be the normal circuit, because the incorrect enable signal EN1 is not sent to the combinational circuit at the next stage.
However, even if the incorrect data signal EN1 is supplied, there is a case that the sequential circuit FF2 latches the enable signal EN1, depending on the differences between the clock signal CLK1 and the clock signal CLK2 in period and phase. For example, as shown in FIG. 1B, if the signal level of the output signal Q1 is “1”, the asynchronous sequential circuit as the verification target circuit sends the correct enable signal EN1 to the combinational circuit at the next stage as the enable signal EN2 when the clock signal CLK2 becomes active (at the time T8). In this case, the asynchronous sequential circuit is determined to be in the normal state, irrespectively of the circuit in an erroneous state. Usually, in order to avoid such a verification error, the verification is carried out under many conditions by changing the phase difference between the clock signal CLK1 and the clock signal CLK2 and the clock periods. Then, since those verification results are statistically processed, the generation of a verification error is suppressed. However, when a difference in the period is large between the clock signal CLK1 and the clock signal CLK2, the period becomes long (between the times T3 and T9 in FIG. 1B) in which the incorrect enable signal EN1 is possibly latched by the sequential circuit FF2. In this case, a possibility that the verification error is generated becomes high, and the possibility that the circuit to be determined to be incorrect is determined to be in the normal state is not small.
A conventional technique for reducing the possibility that the verification error is generated is described in Japanese Patent Application Publication (JP-P2001-229211A: conventional technique 1). A verifying method described in the conventional technique 1 defines whether or not an output data is in the meta stable state based on whether or not the clock signal of a logic circuit is active and whether or not the input data to the logic circuit differs from a previously held value, when the operation of the logic circuit should be verified. In the verifying method described in the conventional technique 1, a predetermined data indicating the meta stable state is outputted from the logic circuit during a predetermined period during which the state is defined as the meta stable state.
FIG. 2A is a timing chart showing the operation of the asynchronous sequential circuit that is simulated by the verifying method described in the conventional technique 1. With reference to FIG. 2A, when detecting the change in the signal level of the enable signal EN1 at the active edge, i.e., the rising edge of the time T3, the sequential circuit FF1 outputs the predetermined value (“1” or “0”) indicating the meta stable state during one period of the clock signal CLK1 (from time T3 to time T5) as the enable signal EN1. At this time, if a time Ta from the time T3 corresponding to the active edge of the sequential circuit FF1 to the active edge of the clock CLK2 is shorter than the one period of the clock signal CLK1, the sequential circuit FF2 latches the data indicating the meta stable state. For example, as shown in FIG. 2A, since the active edge of the clock signal CLK2 exists at a time T4 during a period from the time T3 to the time T5, the sequential circuit FF2 outputs the data indicating the meta stable state during the period from the time T4 to the time T10 (during one period of the clock signal CLK2) as the enable signal EN2.
Since the meta stable state is sent to and latched by the sequential circuit FF2, a verifying apparatus can determine a verification target circuit to be an incorrect circuit. In this way, according to the method described in the conventional technique 1, when the incorrect data Din is inputted, the data indicating the meta stable state is outputted during one period of the clock signal CLK1. Thus, it is possible to reduce the possibility that the sequential circuit FF2 latches the incorrect enable signal EN1. In case of this example, according to the method of the conventional technique 1, even if the clock signal CLK2 becomes active during a period between the times T3 and T5 during which the incorrect enable signal EN1 is supplied, it is possible to latch the data indicating the meta stable state. Thus, it is possible to carry out the asynchronous verification in the meta stable state in a sequential circuit and a combinational circuit that are connected to the sequential circuit FF2 or later.
In the verifying method described in the conventional technique 1, the time in which the asynchronous sequential circuit is defined to be in the meta stable state is determined based on the clock signal CLK1 supplied to the sequential circuit FF1. In the conventional technique 1, the meta stable state and the normal state are switched in accordance with the active edge or rising edge of the clock signal CLK1. Thus, the output period of the data indicating the meta stable state becomes shorter than one period of the clock signal to the sequential circuit on the transmission side. For example, if the period of the clock signal CLK2 is close to the period of the clock signal CLK1, a possibility increases that the time Ta from the active edge of the clock signal CLK1 to the active edge of the clock signal CLK2 is shorter than the one period of the clock signal CLK1. That is, the possibility becomes lower that the clock signal CLK2 becomes active within the period during which the incorrect enable signal EN1 may be latched by the sequential circuit FF2, and thereby the foregoing verification error becomes hard to generate.
However, when the period of the clock signal CLK2 is longer than the period of the clock signal CLK1 so that the difference is large, as shown in FIG. 2B, a possibility increases that the time Ta becomes longer than the one period of the clock signal CLK1. In such a case, the possibility increases that the incorrect enable signal EN1 is latched by the sequential circuit FF2, and propagated as the enable signal EN2. For this reason, in the method described in the conventional technique 1, when the period of the clock signal CLK2 is longer than the period of the clock signal CLK1 so that the difference is larger, there is a case that the asynchronous verification in the meta stable state cannot be carried out in a circuit connected to the later stage of the sequential circuit FF2, even if the phase of the clock signal CLK2 is changed.
Therefore, even in the method of the conventional technique 1, the function simulation for the asynchronous circuit must be executed under the many conditions in which the phases and period of the clock signals CLK1 and CLK2 are changed. For this reason, the description of the asynchronous circuit necessary for the function simulation is complicated, which makes the time of the function simulation long.